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Katedra Mikroelektroniki i Technik Informatycznych Politechniki Lódzkiej; Komputerowe projektowanie ukladów
L2 98 17 530.52M
R13 17 16 1K
*
**************OUTPUT STAGE**************
*
F6 99 50 VA7 1
F5 99 23 VA8 1
D5 21 23 DX
VA7 99 21 0
D6 23 99 DX
E1 99 26 99 15 1
VA8 26 27 0
R16 27 28 25
V5 28 25 0.1V
D4 25 15 DX
V4 24 28 0.1V
D3 15 24 DX
*
***************MODELS USED**************
*
.MODEL DX D(IS=1E-15)
.MODEL JX PJF(BETA=1.25E-5 VTO=-2.00 IS=30E-12)
*
.ENDS
*$
* ///////////////////////////////////////////////////////////////////
* User Notes:
*
* 1. Input resistance (Rin) for these JFET op amps is 1TOhm. Rin is
*  modeled by assuming the option GMIN=1TOhm. If a different (non-
*  default) GMIN value is needed, users may recalculate as follows:
*  Rin=(R1||GMIN+R2||GMIN), where R1=R2,
*  to maintain a consistent Rin model.
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